ISQI CTFL-AcT Q&A - in .pdf

  • CTFL-AcT pdf
  • Exam Code: CTFL-AcT
  • Exam Name: ISTQB Foundation Level - Acceptance Testing
  • PDF Version: V19.35
  • Q & A: 365 Questions and Answers
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NEW QUESTION: 1
A Blue Prism solution works fine when developing and testing it in Process and Object studio but when it is ran in Control Room exceptions occur because of screen elements not being found. What is the most likely cause?
A. The most likely cause for the errors is that the Object Studio action has not been published and therefore cannot be used by the Process in control room.
B. The most likely cause for the errors seen in Control Room is that best practice use of wait stages has not been followed.
C. The most likely cause for the errors is that your application has changed.
D. The most likely cause for the exceptions is that best practice exception handling has not been incorporated into the Process.
Answer: B
Explanation:
Reason: This is because when we are running the process in testing and development phase at time the speed of running the process is slow, that's why it ran properly and when we haven't give the proper wait stage and when the process ran in control room the exception occurs as the process ran in full speed so the process is not having the time to wait.
This is mentioned in the Process creation exercise or Lifecycle exercise.

NEW QUESTION: 2
A switch has been configured with the Vlan dot1q tag native command. Which statement describes what the switch does with untagged frames that it receives on a trunked interface?
A. it drops the untagged frames.
B. Untagged frames are forwarded via the default VLAN
C. Untagged frames are forwarded via the native VLAN
D. The trunked port is put in err-disabled state.
Answer: A

NEW QUESTION: 3
What types of data can the Archiver store?
A. Raw Log only
B. Raw Log. Log Meta. Raw Packet. Packet Meta
C. Raw Log, Log Meta. Packet Meta
D. Raw Log and Log Meta
Answer: A

NEW QUESTION: 4
What benefit does the CAPI feature of POWER8 provide?
A. An implementation of AME on a hardware accelerator
B. An alternative to memory lock base synchronization
C. Shared memory access that is coherent with the system's processor
D. The ability to dispatch multiple virtual machines on a single core at the same time
Answer: A

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